Basics2

Process
VHDL can be used to create both combinatorial (asynchronous) and clock-synchronous "chips".

Most of the time you want to stay away from combinatorial (asynchronous) circuits, because they can contain problems, "glitches", that can be very difficult to find. My simple advice is to just stay away from them.

Clock-synchronous chips can be easily made by combining clock-synchronous VHDL processes. I have found that the following clock-synchronous process template is a good starting point.

Clock-synchronous process template
There are three main sections in the process:

 Reset state of the signals Default values of the signals Override default value on a condition 

--- -- Operations inside the "chip" --- process(reset, clk) begin if (reset='1') then -- Reset state of the signals else -- Rising clock edge if (clk'event and clk='1') then -- Default values of the signals -- Override default value on a condition else end if; end if; end process;

Basics2, using the template
This example combines the "Basics1" with the clock-synchronous process template.

This "chip" simply counts from zero to 15 (4-bit counter) and then it wraps back to zero and continues counting.

Whenever the counter is at 12, then the "output"-signal is set to 1 for the duration of one clock cycle.

--- -- Basics 2 -- -- Entity and architecture -- -- Copyright: Daniel Tisza, 2013, GPLv3 or later --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-- Describe the I/O of this "chip" entity basics2 is

port(		reset : in std_logic;		clk : in std_logic;		output : out std_logic	);

end basics2;

-- Describe the contents of this "chip" architecture rtl of basics2 is	-- Internal signals signal counter : unsigned(3 downto 0);

begin

---	-- Operations inside the "chip" ---	process(reset, clk) begin if (reset='1') then -- Reset state of the signals counter <= to_unsigned(0, 4); output <= '0'; else -- Rising clock edge if (clk'event and clk='1') then -- Default values of the signals counter <= counter + 1; output <= '0'; -- Override default value on a condition if (counter=to_unsigned(12,4)) then output <= '1'; else end if; else end if; end if; end process; end architecture;