Forfun3

How to compile
ghdl -a -v forfun3.vhd

ghdl -e -v forfun3

ghdl -r forfun3 --vcd=out.vcd

How to view waveforms
gtkwave out.vcd

forfun3.vhd
--- -- VHDL for fun 3 -- -- Simple counter -- -- Copyright: Daniel Tisza, 2013, GPLv3 or later --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-- Describe the I/O of this "chip" entity forfun3 is end forfun3;

-- Describe the contents of this "chip" architecture rtl of forfun3 is

-- Counter signals signal count : unsigned(7 downto 0); signal count_full : std_logic; -- Testbench signals signal finished : std_logic; signal clk : std_logic; signal reset : std_logic;

begin

---	-- Simple counter ---	counter_proc : process(reset,clk) begin if (reset='1') then -- Reset state count <= to_unsigned(0,8); count_full <= '0'; else -- Rising edge of the clock if (clk'event and clk='1') then -- Default actions count <= count + 1; count_full <= '0'; -- Counter is full if (count=to_unsigned(4,8)) then -- Override default actions count <= to_unsigned(0,8); count_full <= '1'; else end if; else end if; end if; end process; -- Test bench part

-- Generate reset pulse for global reset testbench_reset_proc : process begin reset <= '1'; wait for 5 us; reset <= '0'; wait; end process;

-- Generate finished signal testbench_finish_proc : process begin -- Initial finished state finished <= '0'; -- Set finished after a delay wait for 50 us; finished <= '1'; -- Wait a while after finishing wait for 3 us; wait; end process; -- Generate clock signal testbench_clock_proc : process begin -- Initial clock signal state clk <= '0'; clockloop : loop -- Clock ticks wait for 1 us; clk <= not(clk); -- Exit loop when finished if (finished='1') then exit; else end if; end loop clockloop; wait; end process; end architecture;