ADC

Analog to digital conversion.

Architectures

 * Flash / Thermometer
 * Successive Approximation
 * Pipeline / Subrange
 * Time-interleaved


 * Folding / Interpolating


 * Delta-Sigma

Flash ADC
The analog input range is divided into N analog reference values. The analog input value is compared with N comparators against each analog reference value. Analog references can be created by a ladder of resistors or capacitors.

Speed depends on the speed of comparators and accuracy depends on the accuracy of analog references and accuracy of comparators.

Successive Approximation
The analog input is sampled and held constant during conversion. The initial digital value is MSB=1, others=0. At each step, the digital value is converted by DAC to an analog candidate value, which is compared with the analog input. If the input is less than the candidate value, the digital value bit is set to 0, otherwise to 1. This is effectively a binary search with N steps.

Requires an overclock, which is N*conversion rate.

Pipeline / Subrange
The analog input is processed in M stages, which creates a latency of M clocks.

Each stage resolves N/K bits and the residue is resolved by later stages. Intermediate DAC is required to subtract the resolved part from the input.

Requires an M*conversion rate overclock, or M number of conversion rate clocks separated by period/M delay.

Time-interleaved
The analog input is sampled by M individual ADCs.