Forfun2

How to compile
ghdl -a -v forfun2.vhd

ghdl -e -v forfun2

ghdl -r forfun2 --vcd=out.vcd

How to view waveforms
gtkwave out.vcd

forfun2.vhd
--- -- VHDL for fun 2 -- -- Adding reset -- -- Copyright: Daniel Tisza, 2013, GPLv3 or later --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-- Describe the I/O of this "chip" entity forfun2 is end forfun2;

-- Describe the contents of this "chip" architecture rtl of forfun2 is

-- Declare signals signal finished : std_logic; signal clk : std_logic; signal reset : std_logic;

begin

-- Generate reset pulse for global reset testbench_reset_proc : process begin reset <= '1'; wait for 5 us; reset <= '0'; wait; end process;

-- Generate finished signal testbench_finish_proc : process begin -- Initial finished state finished <= '0'; -- Set finished after a delay wait for 20 us; finished <= '1'; -- Wait a while after finishing wait for 3 us; wait; end process; -- Generate clock signal testbench_clock_proc : process begin -- Initial clock signal state clk <= '0'; clockloop : loop -- Clock ticks wait for 1 us; clk <= not(clk); -- Exit loop when finished if (finished='1') then exit; else end if; end loop clockloop; wait; end process; end architecture;