Forfun6

How to compile
ghdl -a -v forfun6.vhd

ghdl -e -v forfun6

ghdl -r forfun6 --wave=out.ghw

How to view waveforms
gtkwave out.ghw

forfun6.vhd
--- -- VHDL for fun 6 -- -- State machine -- -- Copyright: Daniel Tisza, 2013, GPLv3 or later --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-- Describe the I/O of this "chip" entity forfun6 is end forfun6;

-- Describe the contents of this "chip" architecture rtl of forfun6 is

-- State machine constants and signals type state_type is (a, b, c, d); signal state : state_type; signal output : std_logic; -- Testbench signals signal finished : std_logic; signal clk : std_logic; signal reset : std_logic;

begin

---	-- State machine ---	stm_proc : process(reset,clk) begin if (reset='1') then -- Reset state state <= a;			output <= '0'; else -- Rising edge of the clock if (clk'event and clk='1') then -- Default actions state <= state; output <= output; -- Decode state case state is					when a => -- Move to state b						state <= b;					when b => -- Move to state c						state <= c;					when c => -- Move to state d						state <= d;						output <= '1'; when d => -- Move to state c						state <= c;						output <= '0'; end case; else end if; end if; end process; -- Test bench part

-- Generate reset pulse for global reset testbench_reset_proc : process begin reset <= '1'; wait for 5 us; reset <= '0'; wait; end process;

-- Generate finished signal testbench_finish_proc : process begin -- Initial finished state finished <= '0'; -- Set finished after a delay wait for 50 us; finished <= '1'; -- Wait a while after finishing wait for 3 us; wait; end process; -- Generate clock signal testbench_clock_proc : process begin -- Initial clock signal state clk <= '0'; clockloop : loop -- Clock ticks wait for 1 us; clk <= not(clk); -- Exit loop when finished if (finished='1') then exit; else end if; end loop clockloop; wait; end process; end architecture;