Forfun7

How to compile
ghdl -a -v forfun7.vhd

ghdl -e -v forfun7

ghdl -r forfun7 --vcd=out.vcd

How to view waveforms
gtkwave out.vcd

forfun7.vhd
--- -- VHDL for fun 7 -- -- Analog signal from RAM -- -- Copyright: Daniel Tisza, 2013, GPLv3 or later --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-- Describe the I/O of this "chip" entity forfun7 is end forfun7;

-- Describe the contents of this "chip" architecture rtl of forfun7 is

-- RAM definitions subtype ram_word_type is std_logic_vector(7 downto 0); subtype ram_addr_type is unsigned(2 downto 0); type ram_type is array(0 to 7) of ram_word_type ; -- RAM signals signal ram : ram_type := (		X"00",		X"11",		X"22",		X"33",		X"44",		X"55",		X"66",		X"77"	); signal ram_addr : ram_addr_type; signal rd_data : ram_word_type; signal wr_data : ram_word_type; signal ram_wr : std_logic; -- Testbench signals signal finished : std_logic; signal clk : std_logic; signal reset : std_logic;

begin

--	-- RAM with single read and write address --	ram_proc : process(clk, ram, ram_wr, ram_addr, wr_data) begin if (clk'event and clk='1') then -- Write to RAM if (ram_wr='1') then ram(to_integer(ram_addr)) <= wr_data; else end if; -- Read from RAM rd_data <= ram(to_integer(ram_addr)); else end if; end process; --	-- Use RAM --	rw_proc : process(reset,clk,ram_addr) begin if (reset='1') then ram_addr <= to_unsigned(0,3); ram_wr <= '0'; wr_data <= X"00"; else if (clk'event and clk='1') then -- Default actions ram_wr <= '0'; ram_addr <= ram_addr + 1; -- Wrap to beginning if (ram_addr=to_unsigned(7,3)) then ram_addr <= to_unsigned(0,3); else end if; -- Trigger writing if (ram_addr=to_unsigned(4,3)) then ram_wr <= '1'; wr_data <= X"AA"; else end if; else end if; end if; end process; -- Test bench part

-- Generate reset pulse for global reset testbench_reset_proc : process begin reset <= '1'; wait for 5 us; reset <= '0'; wait; end process;

-- Generate finished signal testbench_finish_proc : process begin -- Initial finished state finished <= '0'; -- Set finished after a delay wait for 50 us; finished <= '1'; -- Wait a while after finishing wait for 3 us; wait; end process; -- Generate clock signal testbench_clock_proc : process begin -- Initial clock signal state clk <= '0'; clockloop : loop -- Clock ticks wait for 1 us; clk <= not(clk); -- Exit loop when finished if (finished='1') then exit; else end if; end loop clockloop; wait; end process; end architecture;