Forfun5

How to compile
ghdl -a -v forfun5.vhd

ghdl -e -v forfun5

ghdl -r forfun5 --vcd=out.vcd

How to view waveforms
gtkwave out.vcd

forfun5.vhd
--- -- VHDL for fun 5 -- -- PWM -- -- Copyright: Daniel Tisza, 2013, GPLv3 or later --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-- Describe the I/O of this "chip" entity forfun5 is end forfun5;

-- Describe the contents of this "chip" architecture rtl of forfun5 is

-- PWM constants and signals constant count_zero : unsigned(7 downto 0) := "00000000"; constant count_low : unsigned(7 downto 0) := "00000011"; -- 3 constant count_high : unsigned(7 downto 0) := "00000101"; -- 5 signal count : unsigned(7 downto 0); signal pwm : std_logic; -- Testbench signals signal finished : std_logic; signal clk : std_logic; signal reset : std_logic;

begin

---	-- PWM ---	pwm_proc : process(reset,clk) begin if (reset='1') then -- Reset state count <= count_zero; pwm <= '0'; else -- Rising edge of the clock if (clk'event and clk='1') then -- Default actions count <= count + 1; -- Compare count to low and high settings case count is					-- Switch high when count_low => pwm <= '1'; -- Switch low and reset counter when count_high => pwm <= '0'; count <= to_unsigned(0,8); when others => null; end case; else end if; end if; end process; -- Test bench part

-- Generate reset pulse for global reset testbench_reset_proc : process begin reset <= '1'; wait for 5 us; reset <= '0'; wait; end process;

-- Generate finished signal testbench_finish_proc : process begin -- Initial finished state finished <= '0'; -- Set finished after a delay wait for 50 us; finished <= '1'; -- Wait a while after finishing wait for 3 us; wait; end process; -- Generate clock signal testbench_clock_proc : process begin -- Initial clock signal state clk <= '0'; clockloop : loop -- Clock ticks wait for 1 us; clk <= not(clk); -- Exit loop when finished if (finished='1') then exit; else end if; end loop clockloop; wait; end process; end architecture;