Forfun1

How to compile
ghdl -a -v forfun1.vhd

ghdl -e -v forfun1

ghdl -r forfun1 --vcd=out.vcd

How to view waveforms
gtkwave out.vcd

forfun1.vhd
--- -- VHDL for fun 1 -- -- Simple digital clock -- -- Copyright: Daniel Tisza, 2013, GPLv3 or later --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

-- Describe the I/O of this "chip" entity forfun1 is end forfun1;

-- Describe the contents of this "chip" architecture rtl of forfun1 is

-- Declare signals signal finished : std_logic; signal clk : std_logic;

begin

-- Generate finished signal testbench_finish_proc : process begin -- Initial finished state finished <= '0'; -- Set finished after a delay wait for 20 us; finished <= '1'; -- Wait a while after finishing wait for 3 us; wait; end process; -- Generate clock signal testbench_clock_proc : process begin -- Initial clock signal state clk <= '0'; clockloop : loop -- Clock ticks wait for 1 us; clk <= not(clk); -- Exit loop when finished if (finished='1') then exit; else end if; end loop clockloop; wait; end process; end architecture;